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Back-end packaging and test: paid by the second on a tester

What this answers

Which design decisions actually determine what back-end packaging and test will cost?

Once wafers leave the fab they remain a long way from being sellable parts. The back end singulates dies, attaches them to a package, connects them electrically, seals them, then proves each unit works. Two things dominate the economics: how long a device occupies a tester, and which package the customer's thermal and space problem demands. Both are settled by the design, not by the subcontractor performing the work.

Written for: packaging and test operations managers, chip designers making package decisions, supply managers qualifying back-end subcontractors.

Typical production model
Subcontracted conversion of tested wafers into packaged, tested devices, priced largely by equipment occupancy.
Process character
Sequential mechanical and thermal assembly steps closing with electrical testing of every individual unit.
Key inputs
probed wafers from the front end, package substrates, lead frames and bonding wire, moulding compound and die attach materials, test handlers, probers and test programmes
Quality regime
Device qualification and reliability testing per package family, with outgoing quality measured across tested populations.
Capital profile
Equipment-heavy but far less capital-intensive than a fab, with capacity expandable comparatively quickly.
Demand pattern
Follows front-end output with a short lag, swinging on the same cycle amplified by inventory behaviour.
Who buys
integrated device manufacturers, fabless chip companies, foundry customers arranging turnkey supply, module and system assemblers

Tester seconds are the pricing unit

A subcontractor sells occupancy on capital equipment, so the duration of a test programme is the number that matters. Shortening it through better parallelism, smarter sequencing or statistically justified reductions in coverage translates directly into cost. Extending it, or adding temperature-controlled testing, does the reverse. This creates a permanent negotiation between the designer, who wants confidence, and the operations team paying for every extra second across millions of units. Designers who build in test structures and parallel access early hand their operations colleagues a lever that cannot be created afterwards.

Package choice follows the customer's thermal problem

Wire-bonded plastic packages remain the low-cost default. Flip-chip and array packages get chosen when pin count, electrical performance or heat dissipation require them, and each brings different substrate cost, assembly equipment and reliability behaviour. The choice is effectively made by the device and its application rather than by cost preference, since a part dissipating serious power in a confined space has few options. Buyers should recognise that package changes are not simple substitutions, because qualification, board-level reliability testing and sometimes the customer's own assembly process all have to be revisited.

The back end is equipment and labour, not chemistry

Unlike the fab, back-end operations combine expensive but relatively standard equipment with substantial skilled labour across die attach, bonding, moulding, marking, singulation, handling and test cell operation. Cleanliness matters, though not to fab standards, and the buildings cost far less. That different cost structure explains why the back end was the first part of the chain to be widely subcontracted, and why it migrated towards regions with strong technical labour and cheaper construction. Capacity can also be added faster than fab capacity, so back-end constraints usually resolve earlier during a shortage.

Advanced packaging moved real value backwards

As gains from shrinking transistors grew harder to obtain, more performance improvement started coming from how dies are combined: stacking, interposers, separate chiplets connected inside a single package. That shift moved genuine engineering value into a stage long treated as commodity assembly. The consequences show up in capital spending, in the technical depth subcontractors now need, and in a much closer working relationship between designers and packaging engineers. For buyers it means package selection has become a design decision with performance implications rather than a late procurement choice settled on price.

Why back-end capacity clusters where it does

These plants concentrate in a limited number of regions, partly for historical reasons and partly because the combination of skilled technicians, established substrate and materials suppliers, and dependable logistics is difficult to assemble elsewhere. Wafers travel well, so proximity to the fab matters less than proximity to expertise and to downstream assembly customers. That concentration is a recognised supply risk, and attempts to diversify meet the same obstacle every time: equipment can be bought quickly, whereas a trained workforce and a local supplier base take considerably longer to establish. New sites therefore tend to open with an experienced team transplanted from an existing plant.

Frequently asked questions

Why is test such a large share of a chip's total cost?
Because testers are expensive and every device must be exercised individually rather than sampled. The cost equals the tester's hourly rate multiplied by the seconds each part occupies it, divided by how many parts run in parallel. Complex devices need longer programmes and sometimes testing at several temperatures, which multiplies exposure. Reducing it depends on design decisions taken long before production, which is why involving test engineering during design repays itself many times over.
Can a company move its packaging to a different subcontractor?
Yes, but not quickly. The new supplier must qualify the assembly process for that device, demonstrate reliability, and reproduce the test programme on its own equipment, while the customer usually has to requalify the resulting part. Substrates and lead frames may differ, which can shift reliability results. Firms wanting that flexibility qualify a second source deliberately while volumes are stable, rather than attempting it under the pressure of an active supply problem.
What is the practical difference between wafer sort and final test?
Wafer sort exercises dies while still on the wafer, so faulty ones are never packaged and the assembly cost of doomed parts is avoided. Final test checks the completed package, catching faults introduced during die attach, bonding and moulding as well as anything sort missed. Both are needed, and the balance between them is an economic judgement about where a defect costs least to find for that particular device and package.

Data limitations

  • Manufacturing figures are operator-supplied inputs, not market data. GeoBusinessIQ holds no factory costs, production volumes, yields, cycle times, tooling prices or capacity data and does not estimate them — every result reflects only the figures you enter.

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Sources

  • United Nations Industrial Development Organization UNIDO (accessed )
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    Review cadence: Annual, plus on major statutory changes.
  • National Institute of Standards and Technology NIST (accessed )
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    Does not cover: Certification of products, endorsement of vendors, or costs for any specific implementation.
    Why it matters: A United States federal research institute whose public material covers measurement, manufacturing technology and control-system security.
    Review cadence: annual

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